PCIe bus - - -
The introduction of PCIe bus can be regarded as the arrival of the era of the development of traditional parallel bus to high-speed serial bus. In fact, not only the PCI bus to the PCIe bus, but the high speed serial bus replacing the traditional parallel bus is a big trend. Such as ATA to SATA, SCSI to USB, etc...
However, in order to be compatible with previous PCI bus devices, although PCIe is a serial bus, it is no longer compatible with the PCI bus at the physical layer, but it is compatible with the PCI bus at the software layer.
Like many serial buses, PCIe uses a full-duplex transmission design that allows simultaneous transmission and reception of data at the same time. As shown in the figure below, device A and device B are connected through a bidirectional link, and each link supports 1 to 32 lanes. Since it is a serial bus, all data (including configuration information, etc.) is sent in packets.
Like most high-speed connections, PCIe uses differential pairs to send and receive to improve bus performance. An example of a PCIe Lane is shown below:
In addition to the differential bus, PCIe also introduced an embedded clock (Embedded Clock), which means that the sender no longer sends a clock to the receiver, but the receiver can recover the clock from the data Lane through 8b/10b encoding. A simple clock recovery circuit model is shown below:
Note: PCie Gen3 and later versions use 128b/130b encoding.
Another big advantage of PCIe over the PCI bus is its Scalable Performance, which allows you to adjust the bandwidth of your PCIe device based on your application's needs. If you need high bandwidth, use multiple Lanes (such as video cards); if you do not need particularly high bandwidth, you only need one Lane (for example, network card, etc.).
Like the PCI-X bus, PCIe is a point-to-point connection bus rather than a PCI-like shared bus because of its very high transfer speed. However, the PCIe bus system can connect multiple PCIe devices through the Switch, and can also connect traditional PCI and PCI-X devices through the PCIe bridge. The topology of a simple PCIe bus system is shown below:
Note: The Switch here actually contains a number of concepts similar to those in the PCI bus.
The Root Complex in the figure is often referred to as RC or Root. In PCIe Spec, there is no specific detailed definition of Root Complex. From a practical point of view, Root Complex can be understood as the medium for CPU and PCIe bus system communication. The Endpoint is at the very end of the PCIe bus system topology, typically acting as the initiator of the bus operation (similar to the host in the PCI bus) or the terminator (Completes, similar to the slave in the PCI bus). Obviously, the Endpoint can only accept packets from the topological topology or want to send packets in the topological topology.
The so-called Lagacy PCIe Endpoint refers to those devices originally intended to be designed as a PCI-X bus interface, but was changed to a PCIe interface device. Native PCIe Endpoint is a standard PCIe device. Among them, Lagacy PCIe Endpoint can use some operations that are prohibited in Native PCIe Endpoint, such as IO Space and Locked Request. Native PCIe Endpoint is all operated through Memory Map. Therefore, Native PCIe Endpoint is also called Memory Mapped Devices (MMIO Devices).
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