In order to achieve higher bandwidth, the new version of PCI Spec will increase the PCI bus to 64-bit and increase the frequency to 66 MHz, supporting up to 533 MB/s. The following figure depicts a typical 66Mhz, 64-bit PCI system architecture.
As mentioned in the previous article, the PCI bus adopts Reflected-Wave Signaling technology. Therefore, the increase of the bus frequency will inevitably lead to the reduction of the bus load capacity. As a result, the 66MHz 64-bit PCI bus can only support one PCI card device (counted as two PCI devices, one slot and one PCI card). In order to increase the number of PCI devices in the entire system, additional PCI bridges have to be added, which further increases power consumption and increases costs. In addition, the 64-bit PCI bus has increased the number of pins, resulting in a 66 MHz 64-bit PCI bus with reduced stability, placing higher requirements on the design of the PCB and limiting its widespread use.
In addition, since the PCI bus uses a non-registered input, this requires the input signal to have a settling time of at least 3 ns, while the 66 MHz clock has a period of 15 ns. The remaining 12 ns are basically consumed by Reflected-Wave Signaling. Therefore, 66 MHz is basically the upper limit of the frequency of the PCI bus.
In the PCI-X bus, in order to solve the appeal problem, the PCI-X bus takes all the input signals and registers them first. At this time, the requirement for the setup time of the input signal is not so severe, so the PIC-X bus Can operate at higher frequencies (100MHz or even 133MHz).
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