Automobile manufacturers have made unremitting efforts to improve the comfort, safety, convenience, work efficiency and entertainment in the car. In turn, these efforts have promoted the application of various in-car digital technologies.
However, the long development cycle of the automotive industry is difficult to keep up with the latest technological developments, especially the constantly changing automotive intranet specifications, as well as the rapid rise and disappearance of technologies from the consumer market, resulting in higher The engineering design cost and a lot of obsolescence. Adding low-cost targets, extended temperature ranges, high reliability and quality targets, and limited physical board space to these combined factors, as well as the challenges in automotive design, is at best further frustrating. Programmable logic devices (PLD), such as Field Programmable Gate Array (FPGA) and Complex PLD (CPLD), have already appeared on the scene and proved to be a flexible, cost-effective and feasible technical solution that can provide more The traditional hardware solutions adopted have better time to market.
The commercial aspect of car design is becoming more and more important. In a Harvard University study based on 391 different size designs, it was found that the average ASIC SOC design requires 14 to 24 person-months, while the average FPGA design requires six to twelve person-months. This is an average gap of 55% in development time, which means that FPGA design can speed time-to-market for time-critical designs while reducing design costs and overhead. Another major factor that is not usually included in the development cost formula is NRE (Non-Recurring Design Cost) and mask costs. At the 90-nanometer process technology node, the average cost of an ASIC SOC mask set is between US$1 million and US$1.5 million, and these costs are doubled with each reduction in process size. At the same time, due to the increased complexity of designs using these smaller technologies, the chances of chip revisions to ASIC SOC designs due to defects or layout issues have also increased to nearly 40%. * Design engineers must combine these two issues as a potential risk and additional cost. This may be one of the key reasons why the global ASIC design start-up decreased by about 50% between 2000 and 2003 and continued to decline year by year.
Programmable logic devices (PLD) such as FPGA and CPLD provide maximum hardware flexibility. Due to the reprogrammable nature of these devices, developers can enjoy the convenience of updating the design at any time from the prototype to the production stage. Since the PLD design is programmed through the software bit stream, rapid design modification becomes easy and straightforward, and there is no NRE or mask cost.
Because PLDs are scalable in terms of logic density and package migration, they allow designers to make comprehensive modifications while still maintaining the correct pin and logic density. This allows for an excellent cost point per logic price and a number of pins tailored specifically for each design. The PLD design consists of a hardware description language (HDL) to implement logic and C source files for embedded processors. These design source files can be used to implement and reconfigure any PLD, any number of times. Designers can also use existing designs or specific parts of the design to reuse in new projects. This scalability and code reusability avoid obsolescence of products and reduce costs, because developers can quickly and easily upgrade their designs to the latest low-cost devices. We found that there is a common misunderstanding in the field of automotive design that FPGAs are too expensive for production. Five years ago, the price of one million system doors was around US$45. Today, the same one million system gate device sells for less than US$10, while a smaller 100,000 system gate design sells for less than US$3, allowing large-scale integration of multiple components into a single device. It is now fully possible to incorporate FPGAs into full-scale production and achieve the system cost targets required by the automotive market.
The programmable nature of PLDs also provides another level of advantage-in-car programmability and reprogrammability. The in-vehicle programmability support of the equipment can also upgrade its algorithms and functions after the product is deployed. Since the current telematics and video image recognition systems are still in the early stages of research and development, the ability to be upgradeable on-site will be a vital asset. As technology—such as image processing algorithms—improve over time, hardware upgrades can be completed in about a few minutes, without the need to redesign the ASSP or design a new circuit board.
For example, in the instrument cluster and center stack display design, LVDS (low-voltage differential signaling) transceivers have provided automotive designers with the low-noise, high-speed signal interfaces needed to implement flat-panel display (FPD) applications. Recently, the RSDS (Low Swing Differential Signaling) signal interface has been adopted by various display manufacturers. This new signal transmission technology has many advantages over LVDS, including lower dynamic power consumption, further reduced radiated EMI, reduced bus width, high noise suppression, and high throughput rate. Once again, the dynamic nature of PLD gives developers a preferred advantage. PLD supports numerous I/O signal standards, providing developers with the option of integrating emerging technologies such as RSDS in their designs. By quickly adapting to changing standards and adopting the latest and greatest technologies, companies can create time-to-market advantages for themselves and ensure that they remain superior to any competitor.
There are many factors to consider when it comes to the reliability of car design. Although the ISO-TS16949 certification has long been known to the market, designers still need to know more about it. Many companies produce through third-party subcontractors. The designer must ensure that the supplier itself is certified. Otherwise, the provider's design and operating procedures have not reached industry standards. In automotive telematics applications, AEC-Q100 automotive IC stress test qualification and PPAP documentation must also be followed.
Back to the technical side, the use of PLD will also increase reliability. Although LVDS transmitter and receiver pairings have long been available on the market, the use of PLD allows developers to integrate the transceiver in a single device. PLD not only provides various integrated signal transmission functions, but also integrates source and terminal resistors. By eliminating a large number of discrete components, designers can reduce the number of components, thereby simplifying the PCB and realizing a much more reliable signal transmission structure. The end result will be a more cost-effective and reliable system.
PLD not only integrates signal transmission capabilities, but also provides the ability to include the entire system on a single programmable device, which also includes the processor. By putting the entire design on a single chip, designers can reduce the number of components and related connections on the circuit board, thereby forming a scalable, portable and reliable system. For example, color temperature is one of many image enhancement issues that car display developers need to face. Different regions in the world have different requirements for color temperature optimization parameters. By using PLD to create a scalable color temperature adjustment solution that can be used in many geographic areas, supports multiple display types, and only requires minor adjustments to geographically preferred color temperature settings. Platform scalability and design reliability have not been reduced at all, while saving costs.
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