Researchers at the Massachusetts Institute of Technology (MIT) pointed out that today we are all using on-chip busbars and ring topologies, but they may cause more trouble than they can contribute to the value, which also promotes On-chip mesh network (on-chip mesh network) has become the preferred architecture for large-scale parallel processors.
"Future multi-core processors will have to communicate like networked computers by converting information into packets. Each core will have its own router, and they will pass through any of several paths. Packets are sent, and the path selection depends on the overall situation of the network. In short, the ring architecture is much better than the bus architecture, but the performance is better than the non-mesh network. The ring network cannot be expanded to more than 16 Node, "said Li-Shiuan Peh, associate professor of electrical engineering and computer science at MIT.
A mesh network on a chip "can build a grid on all cores, so there are many possible paths between all nodes," Peh said. "And as you continue to expand the number of cores, the latency will be lower. On the other hand, because there are more possible cross-core transmission paths, the bandwidth will also be greatly improved."
Intel used chip mesh networks and integrated routers on the experimental 80-core TeraFLOPS processor a few years ago. However, until recently, Intel used a ring network architecture on the 8-core XeonE5-2600 This is by far the most advanced on-chip network architecture used by the company in mass production chips. However, looking back to the ring topology, Peh said that this architecture is just a temporary solution. Peh claimed that his latest research shows that when developing 16-core or even higher-end processors, like Intel and IBM , ARM, Freescale, Samsung and other multi-core processor manufacturers, have to start using chip network network architecture and integrated routers.
Today, almost all multi-core processors use the traditional bus architecture. This architecture must be equipped with a bus on the core in order to connect with other cores and memory, but Peh said that this bus architecture will be in the four core With the end of the processor, some chip manufacturers have moved to a dual-bus architecture, and Intel's Xeon E5-2600 has also begun to use ring network topology. In the 16-core and more advanced processors in the future, all manufacturers will begin to adopt the Internet-on-a-chip topology.
Peh will present his research results in collaboration with MIT professor Anantha Chandrakasan and doctoral student Sunghyun Park at the Design AutomaTIon Conference in June this year. The chip they showed showed that when using only 300mV voltage fluctuation, the energy consumption of packet switching using the chip Internet topology is less than 38%.
Technical index
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